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r01ds0189ej0120 rev.01.20 page 1 of 10 sep 10, 2012 datasheet sh74572 renesas mcu 1. overview the sh7457 group is a single-chip risc (reduced instruction set computer) microcontroller based on a renesas original risc cpu core. basically the sh7457 group is the same as the sh7456 group. please refer to sh7455 group, sh7456 group user?s manual: hardware rev.1.10 (sep 22, 2011). table 1.1 shows the differences between the sh7456 group and the sh7457 group. * henceforth, the bold letter portion (shaped portion) shows a difference from sh7456 group. table 1.1 products group product model cpu frequency memory capacity package flexray operating temperature (ta) sh7457 sh74572 r5f74572lbg 240 mhz yes -40 to + 105 c sh7455 sh74552 r5f74552kbg yes sh7456 sh74562 r5f74562kbg 160mhz rom: 1 mbyte il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 256 kbytes no -40 to +125c sh7459 sh74593 r5f74593lbg 240mhz rom: 1.5 mbytes il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 512 kbytes prbg0176ga-a yes -40 to +105c 2. details this section shows the details of the differen ce from sh7455 group, sh7456 group user?s manual: hardware rev.1.10 (sep 22, 2011). table 2.1 sh ows the difference between the sh74562 and the sh74572. table 2.1 difference between sh74562 and sh74572 page description 1-4 ? table 1.1 specifications overview: descriptions of cpg product cpu clock (ick) sh74562 160 mhz maximum sh74572 240 mhz maximum 1-6 ? table 1.1 specifications overview: descriptions of flexray product channels of flexray sh74562 none: sh7456 group sh74572 two channels : sh7457 group r01ds0189ej0120 rev.01.20 sep 10, 2012
sh74572 2. details r01ds0189ej0120 rev.01.20 page 2 of 10 sep 10, 2012 page description ? table 1.1 specifications overview: descriptions of operating temperature product model sh74562 ta = ?40c to +125c sh74572 ta = ?40c to + 105 c 1-7 ? table 1.2 products product model flexray sh74562 r5f74562kbg no sh74572 r5f74572lbg yes please refer to appendix a. 1-8 ? figure 1.1 block diagram product sh-4a core clock sh74562 sh-4a core (160 mhz maximum) sh74572 sh-4a core ( 240 mhz maximum) 1-9 1-15 ? figure 1.2 pin arrangement (top transparent view) ? table 1.3 pin functions of pin a6 product a6 pin sh74562 vcc sh74572 vss please refer to appendix b. 14-1 ? table 14.1 relation between i nput frequency and input clock ? figure 14.1 block diagram of cpg product pll frequency multiplier (input to cpu) sh74562 x8. sh74572 x 12 . please refer to appendix c. 14-1 ? table 14.1 relation between i nput frequency and input clock product cpu clock(mhz) sh74562 160. sh74572 240 please refer to appendix c. 15-60 ? table 15.9 minimum of interrupt resp onse time: response time (minimum) product nmi irq peripheral module remarks sh74562 40icyc + s icyc 36icyc + s icyc 32icyc + s icyc when icyc:scyc: pcyc = 4:2:1 sh74572 55 icyc + s icyc 49 icyc + s icyc 43 icyc + s icyc when icyc:scyc: pcyc = 6 :2:1 please refer to appendix d. 38-1 ? table 38.1 absolute maximum ratings product power dissipation (pd) sh74562 1000 mw ,ta = ?40c to +125c sh74572 1200 mw ,ta = ?40c to + 105 c please refer to appendix e. 38-1 ? table 38.1 absolute maximum ratings product operating temperature (topr) sh74562 ?40c to +125c sh74572 ?40c to + 105 c please refer to appendix e.
sh74572 2. details r01ds0189ej0120 rev.01.20 page 3 of 10 sep 10, 2012 page description 38-10 ? table 38.14 dc characteristics - supply current product core supply current (vdd power supply) sh74562 idd is 480 ma(maximum) ick = 160 mhz sh74572 idd is 560 ma(maximum) ick = 240 mhz please refer to appendix f. 38-11 ? 38.3 ac characteristics: descriptions of the timing conditions product the timing conditions of ac characteristics sh74562 ta = ?40c to +125c sh74572 ta = ?40c to + 105 c please refer to appendix g.
sh74572 appendix a r01ds0189ej0120 rev.01.20 page 4 of 10 sep 10, 2012 appendix a section 1 overview 1.2 product line overview table 1.2 lists the products. table 1.2 products product model rom capacity ram capacity package flexray sh74552 r5f74552kbg yes sh74562 r5f74562kbg no sh74572 r5f74572lbg 1 mbyte il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 256 kbytes yes sh74593 r5f74593lbg 1.5 mbyte il memory: 8 kbytes, ol memory: 16 kbytes, and shwyram: 512 kbytes prbg0176ga-a yes
sh74572 appendix b r01ds0189ej0120 rev.01.20 page 5 of 10 sep 10, 2012 appendix b section 1 overview 1.4 pin arrangement figure 1.2 shows the pin arrangement. position o f pin a1 1 wdtovf# xtal md2 md0 md1 pllvcc extal nmi fwe pd3/ pdidata3 pd1/ pdidata1 pd4/ pdidata4 pd9/ pdidata9 pd8/ pdidata8 pd2/ pdidata2 pd10/ pdiwr pd7/ pdidata7 pd6/ pdidata6 pd0/ pdidata0 pd5/ pdidata5 pa0/ to00/ ddb00 pe15/ to27/ pslclr trst# asebrk#/ brkack tdi tdo tck tms reset# mpmd pf0/ crx0 pf1/ ctx0 pf4/ sda/ (crx3) pf5/ scl/ (ctx3) pg0/ mosi0/ to40 pg1/ miso0/ to41 pa2/ to02/ ddb02 pa1/ to01/ ddb01 pa4/ to04/ ddb04 pa3/ to03/ ddb03 pa6/ to06/ ddb06 pa5/ to05/ ddb05 pa8/ to10/ ddb08/ pslclkb pa7/ to07/ ddb07 pa10/ to12/ ddb10/ psldata0 pa9/ to11/ ddb09/ pslclka pa13/ to15/ ddb13/ psldata3 pa12/ to14/ ddb12/ psldata2 pa11/ to13/ ddb11/ psldata1 pb0/ pwmoff0/ dinb0 pb1/ pwmoff1/ dinb1 pc0/ to30/ mosi2/ (irq6) pc2/ to32/ rspck2/ dreq0 pc3/ to33/ ssl20/ irq0 pb3/ pwmoff3/ dinb3 pc5/ to35 pc14 pc6/ clkout/ to36 pllvss pg3/ to43/ ssl00/ (irq7) pg4/ irq2/ to44/ ssl01 pg2/ rspck0/ to42 vss (n.c.) vss vss (n.c.) vss vss vss vss vss vss vss vss avss vcc vss vss vcc vcc vdd vdd vdd vdd vss vcc vcc vss vss vss vss vss vss vcc vcc det3or5 vdd vdd vss vdd vss (n.c.) vdd vdd pl4/ tia10/ (tif0a) pl5/ tia11/ (tif0b) pl8/ tia14/ irq7/ dreq3 pl9/ tia15/ audrevt# pl6/ tia12/ (tif1a) ph8/ drod0/ (to30)/ ddc08/ rts2# ph9/ drod1/ (to31)/ ddc09/ cts2# ph2/ drod10/ to22/ ddc02/ tif1a ph5/ drod13/ to25/ ddc05/ tia01 ph10/ drod2/ (to32)/ ddc10 ph11/ drod3/ (to33)/ ddc11 pl2/ drowr pl3/ irq6 ph7/ drod15/ (to27)/ ddc07/ tia03 ph12/ drod4/ to34/ ddc12 ph13/ drod5/ (to35)/ ddc13 ph14/ drod6/ (to36)/ ddc14/ irq1 ph15/ drod7/ to37/ ddc15 a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 23456789101112131415 123456789101112131415 pc1/ to31/ miso2 avss pm11/ ad0in11 pm13/ ad0in13 pm15/ ad0in15 pm10/ ad0in10 pm2/ ad0in2 pm12/ ad0in12 pm0/ ad0in0 pn1/ ad1in1 p n 0 / a d 1 i n 0 pn5/ ad1in5 pn4/ ad1in4 avcc (n.c.) avrefh avrefh avrefl avrefl avcc pj6/ crx3/ tif2a/ rxd2/ tia04 pj7/ ctx3/ tif2b/ txd2 pj11/ txd0/ ad0end pj12/ sck0/ tclkb/ (irq0) pj13/ rxd1/ miso1 pj10/ rxd0/ pwmoff4/ ad0trg# pj15/ sck1/ pspck1 pj14/ txd1/ mosi1 pj3/ ctx1/ ftxb/ rts0# pj2/ crx1/ frxb pj5/ ctx2/ ftxenb/ sck2 pj4/ crx2/ ftxena/ cts0# pj1/ (ctx0)/ ftxa pj0/ (crx0)/ frxa pm14/ ad0in14 pm6/ ad0in6 pm9/ ad0in9 pm8/ ad0in8 pm4/ ad0in4 avss avss avcc pk14/ audrsyn# pk5/ dinc4/ rxd3 pk13/ audrclk pk12/ audrd3 pk11/ audrd2 ph1/ drod9/ to21/ ddc01/ tif0b ph3/ drod11/ to23/ ddc03/ tif1b ph0/ drod8/ to20/ ddc00/ tif0a pk0/ irq5/ ssl10 ph4/ drod12/ to24/ ddc04/ tia00 ph6/ drod14/ to26/ ddc06/ tia02 p k 6 / t x d 3 pk8/ dreq2 pk10/ audrd1/ cts3# pk9/ audrd0/ rts3# figure 1.2 pin arrangement (top transparent view)
sh74572 appendix c r01ds0189ej0120 rev.01.20 page 6 of 10 sep 10, 2012 appendix c section 14 clock generator (cpg) 14.1 overview table 14.1 lists the relation betwee n input frequency and input clock. table 14.1 relation between input frequency and input clock input frequency (mhz) pll frequency multiplier (input to cpu) cpu clock (mhz) shwy clock (mhz) peripheral clock (mhz) peripheral a clock (mhz) flexray clock (mhz) 20 12 240 80 40 80 80
sh74572 appendix d r01ds0189ej0120 rev.01.20 page 7 of 10 sep 10, 2012 appendix d section15 interrupt controller (intc) 15.5 interrupt response time table 15.9 shows the interrupt response time, which is the interval from when an interrupt request occurs until the interrupt exception handling is started and the start instruction of the interrupt handling is fetched. table 15.9 interrupt response time number of state item nmi irq peripheral module remarks priority determination time 7 pcyc 6 pcyc 5pcyc wait time until the cpu finishes the current sequence s-1 ( 0) icyc interval from when interrupt exception handling begins (saving sr and pc) until a shwy bus request is issued to fetch the start instruction of the interrupt handling 11icyc + 1scyc response time total (s + 10) icyc + 1scyc + 7 pcyc (s + 10) icyc + 1scyc + 6 pcyc (s + 10) icyc + 1scyc + 5pcyc minimum 55 icyc + s icyc 49 icyc + s icyc 43 icyc + s icyc when icyc:scyc: pcyc = 6 :2:1 legend: icyc: period for one cpu clock cycle scyc: period for one shwy clock cycle pcyc: period for one peripheral clock cycle s: number of instruct ion execution states
sh74572 appendix e r01ds0189ej0120 rev.01.20 page 8 of 10 sep 10, 2012 appendix e section 38 electrical characteristics 38.1 absolute maximum ratings table 38.1 shows the absolute maximum ratings. table 38.1 absolute maximum ratings item symbol rating unit remarks v dd vdd ?0.3 to +2.0 v power supply voltage vcc, pllvcc vcc ?0.3 to +6.5 v input voltage vcc power supply related pins vin ?0.3 to vcc +0.3 v analog supply voltage avcc ?0.3 to +6.5 v avrefh ?0.3 to avcc +0.3 v analog reference voltage avrefl ?0.3 to avss +0.3 v avrefh > avrefl analog input voltage van ?0.3 to avcc +0.3 v vss ? pllvss ?0.1 to +0.1 v vss ? avss ?0.1 to +0.1 v vss differential voltage pllvss ? avss ?0.1 to +0.1 v digital input pins imax ?20 to +20 ma maximum input current per pin* 2 (per pin) analog input pins imax ?20 to +20 ma power dissipation pd 1200 mw ta = ?40c to + 105 c operating temperature* 1 topr ?40 to + 105 c storage temperature tstg ?55 to +125 c before assembly [usage notes] operating the mcu in excess of t he absolute maximum ratings may result in permanent damage. be sure to use the mcu in compliance with the connection of power pins, combination conditions of applicable power supply voltages, voltage applicable to each pin, and conditions of output voltage, as specified in the manual. connecting a non-specified power supply or using the mcu at an incorrect voltage may re sult in permanent damage of the mcu or the system that contains the mcu. notes: * 1 this does not guarantee that the micr ocomputer can operate continuously at 85c-plus. consult renesas if the microcomputer is going to be used for 85c-plus applications. * 2 ensure that the current input duration does not exceed 10 ms and that the total curr ent input does not exceed 100 ma.
sh74572 appendix f r01ds0189ej0120 rev.01.20 page 9 of 10 sep 10, 2012 appendix f section 38 electrical characteristics table 38.14 dc characteristics - supply current recommended operating conditions: vcc = pllvcc = 5.0 v 0.5 v/3.3 v 0.3 v, avcc = 5.0 v 0.5 v/3.3 v 0.3 v item symbol min. typ. max. unit measurement conditions core supply current (vdd power supply) i dd ? ? 560 ma ick = 240 mhz system consumption current (vcc power supply) * 1 (including flash memory programming and erasure) i cc ? ? 90 ma pck = 40 mhz pll supply current (pllvcc power supply) i pll ? ? 10 ma during a/d conversion ? ? 10 ma analog supply current (avcc power supply) awaiting a/d conversion i avcc ? ? 1 ma 2 modules, pck = 40mhz during a/d conversion ? ? 4 ma adc reference power supply current (avref) awaiting a/d conversion i avref ? ? 3.5 ma 2 modules, pck = 40mhz notes: * 1 an inrush current of about 100 ma will be caused at power on. ? when the a/d converter is not used, do not leave the avcc, avref, and avss pins open. ? the supply current is measured when v ih min = vcc ? 0.5 v, v il = 0.5 v, with all output pins unloaded.
sh74572 appendix g r01ds0189ej0120 rev.01.20 page 10 of 10 sep 10, 2012 appendix g section 38 electrical characteristics 38.3 ac characteristics ? the timing conditions without specifications are the following : vdd = 1.5 v + 0.15 v, -0.1 v, vcc = pllvcc = 5.0 v 0.5 v/3.3 v 0.3 v, avcc = 5.0 v 0.5 v/3.3 v 0.3 v, avrefh = 4.5 v to avcc/3.0 v to avcc, vss = pllvss = avss = avrefl = 0 v, ta = -40 c to + 105 c when not otherwise specified, the input threshold value is the value under conditions where all module input pins for the same channel are set to the same characteristics. when not otherwise specified, the output driving ability is the value under conditions where all module output pins for the same channel are set to the same characteristics. ? standard values are guaranteed when the output load capacity of the measurement pin is 15 pf to 50 pf. note that the output load capacity of the clkout pin is 15pf to 30pf. cl measured pin : clkout pin = 15 pf to 30 pf : other than the above = 15 pf to 50 pf cmos output figure 38.1 measurement circuit for output switching characteristics cmos input 0.8 vcc 0.2 vcc figure 38.2 input waveform and timing ch eck points at characteristics measurement cmos output note: for details on clkout output timing check points at characteristics measurement, refer to each figure in this section. 0.8 vcc 0.2 vcc figure 38.3 output timing check po ints at characteristics measurement
all trademarks and registered trademarks are t he property of their respective owners. a - 1 revision history sh74572 datasheet description rev. date page summary 1.10 oct 26, 2011 - first edition issued throughout datasheet document number added 1. overview: description changed. from: the sh7457 group is the same as the sh7455 group. to : the sh7457 group is the same as the sh7456 group. table 1.1 products: sh7459 group added. 1 table 2.1 : title and description changed. from: difference between sh74552 and sh74572 to : difference between sh74562 and sh74572 4 appendix a table 1.2 products: sh7459 group added. 1.20 sep 10, 2012 last page the following items added - general precautions in the handing of mpu/mcu products - notice
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products.
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